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dual 5 a, 20 v synchronous step - down regulator with integrated high - side mosf et data sheet adp2325 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2012 analog devices, inc. all rights reserved. features input voltage: 4.5 v to 20 v 1% output accuracy integrated 48 m typical high - side mosfet flexible output configuration dual output: 5 a/5 a parallel single output: 10 a programmable switching frequency: 250 khz to 1.2 mhz external synchronization inpu t with programmable phase shift or internal clock output selectable pwm or pfm mode operation adjustable current limit for small inductor s external compensation and soft star t startup into precharged output supported by adisimpower tm d esign tool applications communications infrastructure networking and servers industrial and instrumentation healthcare and medical intermediate power rail conversion typical application circuit figure 1. general description the adp2325 is a full featured, dual output, step - down dc - to - dc reg ulator based on a current mode architecture. the adp2325 integra tes two high - side power mosfets and two low - side drivers for the exter nal n - channel mosfet s. the two pulse - width mod - ulation (pwm) channels can be configured to deliver dual 5 a outputs or a parallel - to - single 10 a output. the regulator operates from input voltages of 4.5 v to 20 v, and the output voltage can be as low as 0.6 v. the switching f requency can be programmed from 250 khz to 1.2 mhz, or it can be synchronized to an external clock to minimize interference in multirail applications. the dual pwm channels run 180 out of phase, thereby reducing input current ripple as well as reducing th e size of the input capacitor. the bidirectional synchronization pin can be programmed at a 60, 90, or 120 phase shift to provid e for a stackable , multi - phase power solution. the adp2325 can be configured t o operate in pulse frequency modulation (pfm) mode at a light load for higher efficiency or in forced pwm mode for noise sensitive applications. external compensation and soft start provide design flexibility. independent enable inputs and power - good outputs provide reliable power sequencing. to enhance system reliability, the device includes undervoltage lockout (uvlo), overvoltage protection (ovp), overcurrent pro tection, and thermal shutdown. the adp2325 operates over the ?40c to +125c junction temperature range and is available in a 32 - lead lfcsp_wq package. figure 2. efficiency vs. output current at v in = 12 v, f sw = 600 khz bst1 pvin1 sw1 dl1 pgnd sw2 dl2 en1 pgood1 ss1 comp1 fb1 bst2 pvin2 en2 ss2 comp2 fb2 pgood2 gnd sync scfg intvcc rt vdrv v out1 v out2 v in adp2325 l1 l2 c out1 c out2 c in1 m1 m2 r osc c bst1 c ss2 c c2 r c2 r top1 r bot2 r top2 c int c drv trk1 trk2 mode v in c in2 c bst2 r bot1 r c1 c c1 c ss1 10036-001 50 55 60 65 70 75 80 85 90 95 100 0 1.0 2.0 3.0 4.0 0.5 1.5 2.5 3.5 4.5 5.0 efficienc y (%) output current (a) v out = 5.0v v out = 3.3v 10036-002
adp2325 data sheet rev. 0 | page 2 of 32 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 typical applicat ion circuit ............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 functional block diagram .............................................................. 3 specifications ..................................................................................... 4 absolute maximum ratings ....................................................... 6 thermal resistance ...................................................................... 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ............................................. 9 theory of operation ...................................................................... 16 control scheme .......................................................................... 16 pwm mode ................................................................................. 16 pfm mode ................................................................................... 16 precision enable/shutdown ...................................................... 16 separate input voltages ............................................................. 16 internal regulator (intvcc) .................................................. 16 bootstrap circ uitry .................................................................... 17 low - side driver .......................................................................... 17 oscillator ..................................................................................... 17 synchronization .......................................................................... 17 soft start ...................................................................................... 17 peak current - limit and short - circuit protection ................. 17 voltage tracking ......................................................................... 18 parallel operation ....................................................................... 18 power good ................................................................................. 19 overvoltage protection .............................................................. 19 undervoltage lockout ............................................................... 19 thermal shutdown .................................................................... 19 applications information .............................................................. 20 input capacitor selection .......................................................... 20 output voltage setting .............................................................. 20 voltag e conversion limitations ............................................... 20 current - limit setting ................................................................ 20 inductor selection ...................................................................... 20 output capacitor selection ....................................................... 21 lo w - side power device selection ............................................ 22 programming uvlo input ...................................................... 22 compensation components design ....................................... 22 design example .............................................................................. 24 output voltage setting .............................................................. 24 current - limit setting ................................................................ 24 frequency setting ....................................................................... 24 inductor selection ...................................................................... 24 output capacitor selection ....................................................... 24 low - side mosfet selection ................................................... 25 compensation components ..................................................... 25 soft start time programming .................................................. 26 input capacitor selection .......................................................... 26 external components recommendations .................................. 27 typical application circuits ......................................................... 28 packaging and ordering information ......................................... 32 outline dimensions ................................................................... 32 ordering guide .......................................................................... 32 revision history 2 / 12 rev ision 0: initial version
data sheet adp2325 rev. 0 | page 3 of 32 functional block dia gram figure 3. + ? + 0.6v i ss1 ss1 fb1 comp1 amp1 control logic and mosfet driver with anticross protection bst1 sw1 i1 max i1 max hiccup mode nfet1 vdrv dl1 0.7v 0.54v ovp pgood1 pvin1 uvlo en1 current- limit selection oscillator pgnd scfg sync rt clk1 clk2 slope ramp1 slope ramp2 5v regulator en1_buf adp2325 en1_buf en2_buf intvcc pvin1 gnd mode mode_buf skip mode threshold mode_buf skip cmp1 slope ramp1 clk1 ? + vdrv + trk1 + ? + ? 1.2v 4a 1a ocp cmp1 + ? + ? + ? + ? driver driver boost regulator + ? + 0.6v i ss2 ss2 fb2 comp2 amp2 control logic and mosfet driver with anticross protection bst2 sw2 i2 max i2 max hiccup mode nfet2 vdrv dl2 0.7v 0.54v ovp pgood2 pvin2 uvlo en2 current- limit selection en2_buf skip mode threshold mode_buf skip cmp2 slope ramp2 clk2 ? + low-side current sense + trk2 + ? + ? 1.2v 4a 1a ocp cmp2 + ? + ? + ? + ? driver driver boost regulator a cs1 a cs2 10036-003 low-side current sense
adp2325 data sheet rev. 0 | page 4 of 32 specifications pvin1 = pvin2 = 12 v at t j = ?40c to +125c, unless otherwise noted. table 1. parameters symbol test conditions/comments min typ max unit power input (pvinx pins) power input voltage range v pvin 4.5 20 v quiescent current (pvin1 + pvin2) i q mode = gnd, no switching 3 5 ma shutdown current (pvin1 + pvin2) i shdn en1 = en2 = gnd 30 40 a pvinx undervoltage lockout threshold uvlo pvinx rising 4.2 4.4 v pvinx falling 3.5 3.7 v feedback (fbx pins) fbx regulation voltage 1 v fb pvinx = 4.5 v to 20 v 0.594 0.6 0.606 v fbx bias current i fb 0.01 0.1 a error amplifier (compx pins) transconductance g m 370 500 630 s error amplifier source current i source 40 65 90 a error amplifier sink current i sink 45 65 85 a internal regulator (intvcc pin) intvcc voltage 4.75 5 5.25 v dropout voltage i intvcc = 30 ma 300 mv regulator current limit 80 100 120 ma switch node (swx pins) high-side on resistance 2 v bst to v sw = 5 v 48 80 m high-side peak current limit r ilim = floating, v bst to v sw = 5 v 6.4 8 9.6 a r ilim = 47 k, v bst to v sw = 5 v 3.4 4.8 6.2 a low-side negative current-limit threshold voltage 3 50 mv swx minimum on time 3 t min_on 130 ns swx minimum off time 3 t min_off 150 ns low-side driver (dlx pins) rising time 3 t r c dl = 2.2 nf, see figure 23 20 ns falling time 3 t f c dl = 2.2 nf, see figure 26 10 ns sourcing resistor 4 6 sinking resistor 1.4 3 oscillator (rt pin) pwm switching frequency f sw r osc = 100 k 510 600 690 khz pwm frequency range 250 1200 khz synchronization (sync pin) sync input sync configured as input synchronization range 300 1200 khz minimum on pulse width 100 ns minimum off pulse width 100 ns high threshold 1.3 v low threshold 0.4 v sync output sync configured as output frequency on sync pin f clkout f sw khz positive pulse time 100 ns soft start (ssx pins) ssx pin source current i ss 2.5 3.5 4.5 a
data sheet adp2325 rev. 0 | page 5 of 32 parameters symbol test conditions/comments min typ max unit tracking input (trkx pins) trkx input voltage range 0 600 mv trkx -to - fbx offset voltage trkx = 0 mv to 500 mv ? 12 + 12 mv trkx input bias current 100 na power good (pgoodx pins) power - good rising threshold 87 90 93 % power - good hysteresis 5 % power - good deglitch time from fbx to pgoodx 16 clock cycle s pgoodx leakage current v pgood = 5 v 0.1 1 a pgoodx output low voltage i pgood = 1 ma 50 1 00 mv enable (enx pins) enx rising threshold 1.2 1.28 v enx falling threshold 1.02 1.1 v enx source current en voltage below falling threshold 5 a en voltage above rising threshold 1 a mode (mode pin) input high voltage 1.3 v input low voltage 0.4 v thermal shutdown thermal shutdown threshold 150 c thermal shutdown hysteresis 15 c 1 tested in a feedback loop that adjusts v fb to achieve a specified voltage on the compx pin. 2 p in - to - pin measurements . 3 guaranteed by design .
adp2325 data sheet rev. 0 | page 6 of 32 absolute maximum rat ings table 2 . parameter rating pvin1, pvin2, en1, en2 ? 0.3 v to +22 v sw1, sw2 ? 1 v to +22 v bst1, bst2 v sw + 6 v fb1, fb2, ss1, ss2, comp1, comp2, pgood1, pgood2, trk1, trk2, scfg, sync, rt, mode ?0.3 v to +6 v intvcc, vdrv, dl1, dl2 ?0.3 v to +6 v pgnd to gnd ?0.3 v to +0.3 v temperature range operating (junction) ?40c to +125c storage ?65c to +150c soldering conditions jedec j - std -020 thermal resistance ja is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. boundary condition ja is measured using natural convection on a jedec 4 - layer board, and the exposed pad is soldered to the printed circ uit board (pcb) with thermal vias. table 3 . thermal resistance package type ja unit 32 - lead lfcsp_wq 32.7 c/w esd caution s t r e s s es a b o ve t h o s e l i s t e d u n d e r a b s o l u t e m a x i m um r a t i n gs m a y c a u s e p e r m a n e n t dam a g e t o t h e d e v i c e . this is a s t r e s s r a t i n g o n l y ; fu n c t i o n a l o p e r a t i o n o f t h e d ev i c e a t t h e s e o r a n y o t h e r co n d i t i o ns a b o ve t h o s e indi c a t e d i n t h e o p e r a t i o na l s e c t i o n o f t h is s p e c i fi c a t ion is n o t i m p l i e d . e x p o su r e t o a b s o l u te ma x i m u m r a t in g c o n d i t i o n s fo r e x t e n d e d p e r i o d s m a y a ff e c t d e vi c e r e l i a b i l i t y .
data sheet adp2325 rev. 0 | page 7 of 32 pin configuration and fu nction descriptions figure 4. pin configuration (top view) table 4. pin function descriptions pin no. mnemonic description 1 pgood1 power-good output (open drain) for channel 1. a pull-up resistor of 10 k to 100 k is recommended. 2 scfg synchronization configuration input. the scfg pin config ures the sync pin as an input or an output. connect scfg to intvcc to configure sync as an output. connect ing a pull-down resistor to gnd configures sync as an input with various phase shift degrees. 3 sync synchronization. this pin can be configured as an input or an output. when configured as an output, it provides a clock at the switching frequency. when configured as an input, this pin accepts an external clock to which the regulators are synchronized. the phase shift is configured by scfg. note that when sync is configured as an input, the pfm mode is disabled and the device works in continuous conduction mode (ccm) only. 4 gnd analog ground. connect to the ground plane. 5 intvcc internal 5 v regulator output. the ic control circuits are powered from this voltage. place a 1 f ceramic capacitor between intvcc and gnd. 6 rt connect a resistor between rt and gnd to program the switching frequency from 250 khz to 1.2 mhz. 7 mode mode selection. when this pin is connected to intvcc, th e pfm mode is disabled and the regulator works only in ccm. when this pin is connected to ground, the pfm mode is enabled. if the low-side device is a diode, the mode pin must be connected to ground. 8 pgood2 power-good output (open drain) for channel 2. a pull-up resistor of 10 k to 100 k is recommended. 9 fb2 feedback voltage sense input for channel 2. connect fb2 to a resistor divider from the channel 2 output voltage, v out2 . connect fb2 to intvcc for parallel applications. 10 comp2 error amplifier output for channel 2. connect an rc network from comp2 to gnd. connect comp1 and comp2 together for parallel applications. 11 ss2 soft start control for channel 2. to program the soft start time, connect a capacitor from ss2 to gnd. for parallel applications, ss2 remains open. 12 trk2 tracking input for channel 2. to track a master voltage, connect this pin to a resistor divider from the master voltage. if the tracking function is not used, connect trk2 to intvcc. 13 en2 enable pin for channel 2. an external resistor divider can be used to set the turn-on th reshold. when not using the enable pin, connect en2 to pvin2. 14, 15 pvin2 power input for channel 2. connect pvin2 to the inp ut power source, and connect a bypass capacitor between pvin2 and ground. 16, 17 sw2 switch node for channel 2. 18 bst2 supply rail for the gate drive of channel 2. place a 0.1 f capacitor between sw2 and bst2. 19 dl2 low-side gate driver output for channel 2. connect a resistor between dl2 and pgnd to program the current- limit threshold of channel 2. 20 vdrv low-side driver supply input. connect vdrv to intvcc. place a 1 f ceramic capacitor between the vdrv pin and pgnd. 21 pgnd driver power ground. connect to the source of the synchronous n-channel mosfet. 22 dl1 low-side gate driver output for channel 1. connect a resistor between dl1 and pgnd to program the current- limit threshold of channel 1. 23 bst1 supply rail for the gate drive of channel 1. place a 0.1 f capacitor between sw1 and bst1. 1s w 1 2 bst1 3 dl1 4 pgnd 5 vdrv 6 dl2 7 bst2 8 sw2 24 23 22 21 20 19 18 17 pgood1 notes 1. the exposed pad should be soldered to an external gnd plane. scfg sync gnd intvcc rt mode pgood2 9 10 11 12 13 14 15 16 fb2 comp2 ss2 trk2 en2 pvin2 pvin2 sw2 32 31 30 29 28 27 26 25 fb1 comp1 ss1 trk1 en1 pvin1 pvin1 sw1 top view (not to scale) adp2325 10036-004
adp2325 data sheet rev. 0 | page 8 of 32 pin no. mnemonic description 24, 25 sw1 switch node for channel 1. 26, 27 pvin1 power input for channel 1. these pins are the power inputs for channel 1 and provide power for the internal regulator. connect to the input power source and connect a bypass capacitor between pvin1 and ground. 28 en1 enable pin for channel 1. an external resistor divider ca n be used to set the turn-o n threshold. when not using the enable pin, connect en1 to pvin1. 29 trk1 tracking input for channel 1. to track a master voltage, connect this pin to a resistor divider from the master voltage. if the tracking function is not used, connect trk1 to intvcc. 30 ss1 soft start control for channel 1. to program the soft start time, connect a capacitor from ss1 to gnd. 31 comp1 error amplifier output for channel 1. connect an rc network from comp1 to gnd. connect comp1 and comp2 together for parallel applications. 32 fb1 feedback voltage sense input for channel 1. connect fb1 to a resistor divider from the channel 1 output voltage, v out1 . n/a 1 ep exposed pad. solder the exposed pad to an external gnd plane. 1 n/a means not applicable.
data sheet adp2325 rev. 0 | page 9 of 32 typical performance characteristics t a = 25 c, v in = 12 v, v out = 3.3 v, l = 2.2 h, c out = 2 100 f, f sw = 600 khz, unless otherwise noted. figure 5 . efficiency at v in = 12 v, f sw = 600 khz, fpwm figure 6 . efficiency at v in = 12 v, f sw = 600 khz, fpwm and pfm figure 7 . efficiency at v in = 5 v, f sw = 600 khz, fpwm figure 8 . efficiency at v in = 12 v, f sw = 300 khz, fpwm figure 9 . efficiency at v in = 12 v, f sw = 300 khz, fpwm and pfm figure 10 . efficiency at v in = 18 v, f sw = 300 khz, fpwm 50 55 60 65 70 75 80 85 90 95 100 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 efficienc y (%) output current (a) inductor: fdve1040-2r2m mosfet: FDS8880 v out = 5.0v v out = 3.3v v out = 2.5v v out = 1.8v v out = 1.5v v out = 1.2v 10036-005 efficienc y (%) output current (a) 0 10 20 30 40 50 60 70 80 90 100 0.01 0.1 1 inductor: fdve1040-2r2m mosfet: FDS8880 v out = 5.0v, fpwm v out = 3.3v, fpwm v out = 5.0v, pfm v out = 3.3v, pfm 10036-006 50 55 60 65 70 75 80 85 90 95 100 efficienc y (%) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 output current (a) inductor: fdve1040-1r5m mosfet: FDS8880 v out = 3.3v v out = 2.5v v out = 1.8v v out = 1.5v v out = 1.2v 10036-007 efficienc y (%) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 output current (a) 50 55 60 65 70 75 80 85 90 95 100 inductor: fdve1040-4r7m mosfet: FDS8880 v out = 5.0v v out = 3.3v v out = 2.5v v out = 1.8v v out = 1.5v v out = 1.2v 10036-008 0 10 20 30 40 50 60 70 80 90 100 0.01 0.1 1 efficienc y (%) output current (a) v out = 5.0v, fpwm v out = 3.3v, fpwm v out = 5.0v, pfm v out = 3.3v, pfm inductor: fdve1040-4r7m mosfet: FDS8880 10036-009 efficienc y (%) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 output current (a) 50 55 60 65 70 75 80 85 90 95 100 inductor: fdve1040-4r7m mosfet: FDS8880 v out = 5.0v v out = 3.3v v out = 2.5v v out = 1.8v v out = 1.5v v out = 1.2v 10036-010
adp2325 data sheet rev. 0 | page 10 of 32 figure 11 . shutdown current vs. v in figure 12 . uvlo threshold vs. temperature figure 13 . en source current vs. temperature at v en = 1.5 v figure 14 . quiescent current vs. v in figure 15 . en threshold vs. temperature figure 16 . en source current vs. temperature at v en = 1 v 10 15 20 25 30 35 40 4 6 8 10 12 14 16 18 20 shutdown current (a) t j = ?40c t j = +25c t j = +125c v in (v) 10036-0 1 1 3.5 3.6 3.7 3.8 3.9 4.0 4.1 4.2 4.3 4.4 4.5 ?40 ?20 0 20 40 60 80 100 120 uvlo threshold (v) rising falling temper a ture (c) 10036-012 0.90 0.92 0.94 0.96 0.98 1.00 1.02 1.04 1.06 1.08 1.10 ?40 ?20 0 20 40 60 80 100 120 en source current (a) temper a ture (c) 10036-013 2.80 2.85 2.90 2.95 3.00 3.05 3.10 4 6 8 10 12 14 16 18 20 quiescent current (ma) v in (v) t j = ?40c t j = +25c t j = +125c 10036-014 1.00 1.05 1.10 1.15 1.20 1.25 1.30 ?40 ?20 0 20 40 60 80 100 120 enable threshold (v) rising falling temper a ture (c) 10036-015 4.70 4.75 4.80 4.85 4.90 4.95 5.00 5.05 5.10 5.15 5.20 5.25 5.30 ?40 ?20 0 20 40 60 80 100 120 en source current (a) temper a ture (c) 10036-016
data sheet adp2325 rev. 0 | page 11 of 32 figure 17. feedback voltage vs. temperature figure 18. frequency vs. temperature figure 19. mosfet r dson vs. temperature figure 20. transconductance (g m ) vs. temperature figure 21. intvcc voltage vs. v in figure 22. ssx pin source current vs. temperature 596 597 598 599 600 601 602 603 604 ?40 ?20 0 20 40 60 80 100 120 feedback v o ltage (mv) temperature (c) 10036-017 540 560 580 600 620 640 660 ?40?200 20406080100120 frequency (khz) r osc = 100k ? temperature (c) 10036-018 30 35 40 45 50 55 60 65 70 75 80 ?40 ?20 0 20 40 60 80 100 120 mosfet resistor (m ? ) temperature (c) 10036-019 400 420 440 460 480 500 520 540 560 580 600 ?40 ?20 0 20 40 60 80 100 120 transconductance (s) temperature (c) 10036-020 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 4 6 8 101214161820 intvcc v o ltage (v) v in (v) 10036-021 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 ?40 ?20 0 20 40 60 80 100 120 ssx pin source current (a) temperature (c) 10036-022
adp2325 data sheet rev. 0 | page 12 of 32 figure 23 . low - side driver rising edge waveform, c dl = 2.2 nf figure 24 . peak current - limit threshold vs. temperature, r ilim = floating figure 25 . continuous conduction mode (ccm) figure 26 . low - side driver falling edge waveform, c dl = 2.2 nf figure 27 . peak current - limit threshold vs. temperature, r ilim = 47 k? figure 28 . discontinuous conduction mode (dcm) 2 ch1 5v ch2 2v m20ns a ch1 4v 1 t 40.4% sw dl 10036-023 6.5 7.0 7.5 8.0 8.5 9.0 9.5 ?40 ?20 0 20 40 60 80 100 120 peak current limit (a) temper a ture (c) 10036-024 ch1 10mv ch2 10v m 1 s a ch2 4.6v 1 4 2 t 42.6% ch4 2 a ? b w 10036-028 v out (ac) sw i l ch1 5v ch2 2v m20ns a ch2 4.04v 1 2 t 40.4% sw dl 10036-026 temper a ture (c) 3.5 4.0 4.5 5.0 5.5 6.0 6.5 ?40 ?20 0 20 40 60 80 100 120 peak current limit (a) 10036-025 ch1 10mv m 1 s a ch2 8.4v 1 4 2 t 47.2% ch4 1a ? b w ch2 10v v out (ac) sw i l 10036-029
data sheet adp2325 rev. 0 | page 13 of 32 figure 29. power saving mode figure 30. soft start with full load figure 31. load transient response, 1 a to 4 a figure 32. dual phase, single output, v out = 3.3 v, i out = 10 a figure 33. soft start with precharged output figure 34. line transient response, v in from 8 v to 14 v, i out = 5 a ch1 100mv m 1ms a ch2 8.4v 1 4 2 t 47.2% ch4 1a ? b w ch2 10v i l sw v out (ac) 10036-032 ch1 2v ch2 5v ch3 10v m 1ms a ch3 3.4v 3 1 2 4 t 20.2% ch4 5a ? b w pgood i out en v out 10036-030 ch1 100mv m 200s a ch4 3.4a 1 4 t 20.2% ch4 2a ? b w i out v out (ac) 10036-031 b w b w ch2 10v ch4 2a ch1 10v ch3 2a m 1s a ch2 5.6v 1 2 4 t 50.4% ?? sw1 sw2 i l1 i l2 10036-040 ch1 2v ch2 5v ch3 10v m 1ms a ch3 3.4v 3 1 2 4 t 20.2% ch4 2a ? b w pgood i l en v out 10036-033 ch1 20mv m 400s a ch3 11.5v 1 3 t 73.8% b w ch3 5v b w v in v out (ac) 10036-034
adp2325 data sheet rev. 0 | page 14 of 32 figure 35 . output short figure 36 . external synchronization with 60 phase shift figure 37 . external synchronization with 120 phase shift figure 38 . output short recovery figure 39 . external synchronization with 90 phase shift figure 40 . sync pin configured as output ch1 2v m 10 ms a ch1 1.32v 1 4 2 t 19.8% ch4 5a ? b w ch2 10v sw i l v out 10036-035 ch3 5v ch2 10v ch1 10v m 1 s a ch3 2.8v 3 1 2 t 50.4% sync sw1 sw2 10036-036 ch2 10v ch3 5v ch1 10v m 1 s a ch3 2.8v 1 2 3 t 50.4% sync sw1 sw2 10036-037 4 m 10 ms a ch1 1.32v t 60.2% ch4 5a ? b w ch2 10v ch1 2v 1 2 sw i l v out 10036-038 ch3 5v ch2 10v ch1 10v m 1 s a ch3 2.8v 3 1 2 t 50.4% sync sw1 sw2 10036-039 ch3 5v ch2 10v ch1 10v m 1 s a ch3 2.5v 3 1 2 t 50.0% sync sw1 sw2 10036-048
data sheet adp2325 rev. 0 | page 15 of 32 figure 41 . coincident tracking figure 42 . thermal derating performance at 110c case temperature b ased on adp2325 - evalz board figure 43 . ratiometric tracking figure 44 . thermal derating performance at 110c case temperature b ased on adp2325 - evalz board ch2 1v m 1 ms a ch1 1.56v 2 t 50.4% b w b w ch1 1v v master v slave 10036-057 0 1 2 3 4 5 6 25 40 55 70 85 100 output current of ch2 (a) ambient temper a ture (c) ch1 = 0a ch1 = 1a ch1 = 2a ch1 = 3a ch1 = 4a ch1 = 5a v out1 = 1.2v v out2 = 3.3v f sw = 500khz 10036-058 ch2 1v m 1 ms a ch1 1.58v 2 t 49.8% b w b w ch1 1v v master v slave 10036-059 0 1 2 3 4 5 6 output current of ch1 (a) 25 40 55 70 85 100 ambient temper a ture (c) v out1 = 1.2v v out2 = 3.3v f sw = 500khz 10036-060 ch2 = 0a ch2 = 1a ch2 = 2a ch2 = 3a ch2 = 4a ch2 = 5a
adp2325 data sheet rev. 0 | page 16 of 32 theory of operation the adp2325 is a full featured, dual output, step-down dc-to-dc regulator based on a current mode architecture. it integrates two high-side power mosfets and two low-side drivers for external mosfets. the adp2325 is designed for high performance applications that require high efficiency and design flexibility. the adp2325 can operate with an input voltage from 4.5 v to 20 v and can regulate the output voltage to as low as 0.6 v. additional features for flexible design include programmable switching frequency, programmable soft start, external compen- sation, independent enable inputs, and power-good outputs. control scheme the adp2325 uses a fixed frequency, current mode pwm control architecture during medium to full loads, but shifts to a power save mode (pfm) at light loads when the pfm mode is enabled. the power save mode reduces switching losses and boosts effi- ciency under light loads. when operating in the fixed frequency pwm mode, the duty cycle of the integrated n-channel mosfet (referred to inter- changeably as nfet or mosfet) is adjusted, this, in turn, regulates the output voltage. when the device operates in power save mode, the switching frequency is adjusted to regu late the output voltage. pwm mode in pwm mode, the adp2325 operates at a fixed frequency set by an external resistor. at the start of each oscillator cycle, the high-side nfet turns on, placing a positive voltage across the inductor. the inductor current increases until the current sense signal crosses the peak inductor current threshold, turning off the high-side nfet and turning on the low-side nfet (diode). this places a negative voltage across the inductor, causing a reduction in the inductor current. the low-side nfet (diode) stays on for the remainder of the cycle or until the inductor current reaches zero. pfm mode to enable the pfm mode, pull the mode pin to ground. when the compx voltage is below the pfm threshold voltage, the device enters the pfm mode. when the device enters the pfm mode, it monitors the fbx voltage to regulate the output voltage. because the high-side and low- side nfets are turned off, the load current discharges the output capacitor causing the output voltage to drop. when the fbx voltage drops below 0.605 v, the device starts switching and the output voltage increases as the output capacitor is charged by the inductor current. when the fbx voltage exceeds 0.62 v, the device turns off both the high-side and low-side nfets until the fbx voltage drops to 0.605 v. in the pfm mode, the output voltage ripple is larger than the ripple in the pwm mode. precision enable/shutdown the adp2325 has two independent enable pins (en1 and en2), one for each channel. the enx pin has an internal pull- down current source of 5 a to provide a default turn-off whenever an enx pin is open. when the voltage on the en1 or en2 pin exceeds 1.2 v (typical), channel 1 (per the en1 pin) or channel 2 (per the en2 pin) is enabled and the internal pull-down current source at the en1 or en2 pin is reduced to 1 a, which allows the user to program the uvlo lockout of the input voltage. when the voltage on the en1 or en2 pin drops below 1.1 v (typical), channel 1 or channel 2 turns off. when en1 and en2 are both below 1.1 v, all of the internal circuits turn off and the device enters the shutdown mode. separate input voltages the adp2325 supports two separate input voltages. this means that the pvin1 and pvin2 voltages can be connected to two different supply voltages. in these types of applications, because the pvin1 voltage provides the power supply for the internal regu- lator and control circuitry, the pvin1 voltage must be above the uvlo voltage before the pvin2 voltage begins to rise. this feature allows for a cascading supply operation, as shown in figure 45 where pvin2 is sourced from the channel 1 output. in this configuration, the channel 1 output voltage needs to be high enough to maintain channel 2 in regulation, and the channel 1 output voltage must be higher than the input voltage uvlo threshold. figure 45. cascading supply operation internal regulator (intvcc) the internal regulator provides a stable voltage supply for the internal control circuits and a bias voltage for the low-side gate drivers. it is recommended that a 1 f ceramic capacitor be placed between intvcc and gnd. the internal regulator also includes a current-limit circuit for protection. the internal regulator is active when either of the channels is enabled. the pvin1 pin provides power for the internal regulator, which is used by both channels. sw2 dl2 l2 pvin2 sw1 dl1 pgnd c out1 m1 l1 pvin1 adp2325 v in v out1 v out2 c out2 m2 10036-041
data sheet adp2325 rev. 0 | page 17 of 32 bootstrap circuitry the adp2325 integrates the boot regulators to provide the gate drive voltage for the high-side nfets. the regulators generate 5 v bootstrap voltages between the bstx and the swx pins. it is recommended that an x7r or x5r, 0.1 f ceramic capacitor be placed between the bstx and the swx pins. low-side driver the dlx pin provides the gate drive for the low-side n-channel mosfet. internal circuitry monitors the gate driver signal to ensure break-before-make switching to prevent crossconduction. the vdrv pin provides the power supply to the low-side drivers. it is limited to a 5.5 v maximum input; placing a 1 f ceramic capacitor close to this pin is recommended. oscillator a resistor from rt to gnd programs the switching frequency according to the following equation: f sw [khz] = ] k [ 00060 osc r , a 200 k resistor sets the frequency to 300 khz, and a 100 k resistor sets the frequency to 600 khz. figure 46 shows the typical relationship between f sw and r osc . figure 46. f sw vs. r osc synchronization the sync pin can be configured as an input or an output by setting the scfg pin, as shown in table 5. table 5. scfg configuration scfg sync phase shift intvcc output 0 gnd input 90 180 k to gnd input 120 100 k to gnd input 60 when the sync pin is configured as an output, it generates a clock with a frequency that is equal to the internal switching frequency. when the sync pin is configured as an input, the adp2325 syn- chronizes to the external clock that is applied to the sync pin, and the internal clock must be programmed lower than the external clock. the phase shift can be programmed by the scfg pin. when working in synchronization mode, the adp2325 disables the pfm mode and works only in the ccm mode. soft start use the ssx pins to program the soft start time. place a capacitor between ssx and gnd; an internal current charges this capacitor to establish the soft start ramp. the soft start time can be calculated using the following equation: ss ss ss i c t ? ? v6.0 where: c ss is the soft start capacitance. i ss is the soft start pull-up current (3.5 a). if the output voltage is precharged prior to power-up, the adp2325 prevents the low-side mosfet from turning on until the soft start voltage exceeds the voltage on the fbx pin. during soft start, the adp2325 uses frequency foldback to prevent output current runaway. the switching frequency is reduced according to the voltage present at the fbx pin, which allows more time for the inductor to discharge. the correlation between the switching frequency and the fbx pin voltage is listed in table 6. table 6. fbx pin voltage and switching frequency fbx pin voltage switching frequency v fb 0.4 v f sw 0.4 v > v fb 0.2 v 1/2 f sw v fb < 0.2 v 1/4 f sw peak current-limit and short-circuit protection the adp2325 uses a peak current-limit protection circuit to prevent current runaway. place a resistor between dlx and pgnd to program the peak current-limit value, as listed in table 7. the programmable peak current-limit threshold feature allows for the use of a small size inductor for low current applications. table 7. peak current-limit threshold setting r ilim peak current-limit threshold floating 8 a 47 k 4.8 a the adp2325 uses hiccup mode for overcurrent protection. when the peak inductor current reaches the current-limit threshold, the high-side mosfet turns off and the low-side driver turns on until the next cycle while the overcurrent counter is incremented. 200 300 400 600 800 500 700 900 1000 1100 1200 50 90 130 170 210 70 110 150 190 230 250 switching frequen c y (khz) r osc (k ? ) 10036-042
adp2325 data sheet rev. 0 | page 18 of 32 if the overcurrent counter reaches 10, or if the fbx pin voltage falls to 0.2 v after the soft start, the device e nters hiccup mode. during this mode, the high - side mosfet and low - side driver are both turned off. the device remains in this mode for seven soft start cycle s and then attempts to restart from soft start. if the current - limit fault is cleared, the device resumes normal operation; otherwise, it reenters hiccup mode. the adp2325 provides a negative current limit. when the low - side fet voltage exceed s the negative current - limit threshold voltage (50 mv typical), the low - side f et turn s off immediately for the re mainder of this cycle. both the high - side and low - side fet s turn off until the next cycle. in some cases, the input voltage (pvin) ramp rate is too slow or the output capaci tor is too large to support the set regulation voltage during the soft start , causing the device to enter the hiccup mode. to prevent such cases, use a resistor divider at the enx pin to program the uvlo of the input voltage or use a longer soft start time. voltage tracking the adp2325 has a tracking input, trkx, that allows the output voltage to track an external (master) voltage. voltage tracking allows power sequencing applicable for fpgas, dsps, and asics, which may require a power sequence b etween the core and the i/o voltages. the internal error amplifier includes three positive inputs: the internal reference voltage, the soft start voltage, and the tracking input voltage. the error amplifier regulates the feedback voltage to the lowest of t he three voltages. to track a master voltage, connect the trkx pin to a resistor divider from the master voltage , as shown in figure 47. figure 47 . voltage tracking coincident tracking a common application is coincident tracking, which is shown in figure 48 . coincident tracking limits the slave output voltage to be the same as the master voltage until it reaches regu lation. to enable coincident tracking, set r trk_top = r top and r trk_bot = r bot . figure 48 . coincident tracking ratiometric tracking in r atiometric tracking , t he slave output voltage is limited to a frac - tion of the master voltage. in this application, the slave and master voltages reach the ir final value s at the same time (see figure 49 ) . figure 49 . ratiometric tracking the ratio of the slave output voltage to the master voltage is a function of the two dividers, as follows: bot trk top trk bot top master slave r r r r v v _ _ 1 1 + + = the final trkx pin voltage must be higher than 0.54 v. if the tracking function is not used, connect the trkx pin to intvcc. parallel operation the adp2325 supports a 2 - phase parallel operation to provide a single output of 1 0 a. to configure the adp2325 as a 2 - phase single output 1. connect the fb2 pin to intvcc, thereby disabling the channel 2 error amplifier. 2. connect comp1 to comp2 and connect en1 to en2. 3. use ss1 to set the soft start time and keep ss2 open. during parallel operation, the voltages of pvin1 and pvin2 should be the same. fbx trkx swx adp2325 v master r trk_top r trk_bot v slave r top r bot 10036-043 time voltage v master v slave 10036-044 time voltage v master v slave 10036-045
data sheet adp2325 rev. 0 | page 19 of 32 power good the power - good (pgoodx) pin is an active high, open - drain output that indicates whether the regulator output voltage is within regulation. logic h igh indicates that the voltage at the fbx pin (and, therefore , the output voltage) is above 90 % of the reference voltage. l ogic l ow indicates that the voltage at the fbx pin (and, therefore , the output voltage) is below 85 % of the reference voltage. there is a 16- cycle deglitch time between fbx and pgoodx. overvoltage protecti on the adp2325 provides an ovp feature to protect the system against an output shorting to a higher voltage supply or for when a strong load transient occurs. if the feedback voltage increases to 0.7 v, the internal high - side mosfet and low - side driver turn off until the voltage at the fbx pin is red uce d to 0.63 v, at which t ime the adp2325 resumes normal operation. undervoltage lockout the uvlo threshold is 4.2 v with 0.5 v hysteresis to prevent power - on glitches on the device . when the pvin1 or pvin2 voltage rises above 4.2 v , channel 1 or channel 2 is enabled and the soft start period initiates. when either pvin1 or pvin2 drops below 3.7 v, it turns off channel 1 or channel 2, respectively. thermal shutdown in the event that the a dp2325 junction temperature exceeds 150 c, the thermal shutdown circuit turns off the regulator. a 15 c hysteresis is included so that the adp2325 does not recover from thermal shutdown until the on - chip tempera ture drops below 13 5 c. upon recovery, soft start initiate s prior to normal operation.
adp2325 data sheet rev. 0 | page 20 of 32 application s information input capacitor sele ction the input decoupling capacitor attenuates high fre quency noise on the input and acts as an energy reservoir. this capacitor should be a ceramic capacitor in the range of 10 f to 47 f and must be placed close to the pvinx pin. the loop composed of this input capacitor, high - side nfet, and low - side nfet m ust be kept as small as possible. the voltage rating of the input capacitor must be greater than the maximum input voltage. ensure that t he rms current rating of the input capacitor is larger than th at expressed in following equation: ( ) d d i i out _rms in c ? = 1 output voltage setti ng the output voltage of the adp2325 can be set by an external resistor divider using the following equation: ? ? ? ? ? ? ? ? + = bot top out r r v 1 6 . 0 to limit output voltage accuracy degradation due to fbx pin bias curre nt (0.1 a maximum) to less than 0.5% (maximum) , ensure that r bot is less than 30 k?. table 8 provide s the recom - mended resistor divide r for various output voltage options. table 8 . resistor divider for various output voltages v out (v) r top , 1% (k ) r bot , 1% (k ) 1.0 10 15 1.2 10 10 1.5 15 10 1.8 20 10 2.5 47.5 15 3.3 10 2.21 5.0 22 3 voltage conversion l imitations the minimum output voltage for a given input voltage and switching frequency is limit ed by the minimum on time. the minimum on time of the adp2325 is typically 130 ns. the minimu m output voltage in ccm mode at a given input voltage and frequency can be calculated using the following equation: v out_min = v in t min_on f sw ? ( r dson1 ? r dson2 ) i out_min t min_on f sw ? ( r dson2 + r l ) i out_min where: v out_min is the minimum output voltage. t min_on is the minimum on time. i out_min is the minimum output current. f sw is the switching frequency. r dson1 is the high - side mosfet on resistance. r dson2 is the low - side mosfet on resistance. r l is the series resistance of the output inductor. the maximum output voltage for a given input voltage and switching frequency is also limited by the minimum off time and the maximum duty cycle. the minimum off time is typically 150 ns and the maximum duty is typically 90% in the adp2325 . the maximum output voltage that is limited by the minimum off time at a given input voltage and frequency can be calculated using the following equation: v out_max = v in (1 ? t min_off f sw ) ? ( r dson1 ? r dson2 ) i out_max (1 ? t min_off f sw ) ? ( r dson2 + r l ) i out_max where: v out_max is the maximum output voltage. t min_off is the minimum off time. i out_max is the maximum output current. the maximum output voltage that is limited by the maximum duty cycle at a given input voltage can be calculated using the following equation: v out_max = d max v in where d max is the maximum duty cycle . as the previous equa tions demonstrate , reducing the switching frequency alleviates the minimum on time and minimum off time limitation. current - limit setting the adp2325 has t w o selectable current - limit thresholds. make sure that the selected current - limit value is larger than the peak current of the inductor, i pe ak . inductor selection the inductor value is determined by the operating frequency, input voltage, output voltage, and inductor ripple current. using a small inductor provides faster transient response but degrades efficiency d ue to larger inductor ripple current, whereas a large inductor value provides smaller ripple current and better effi - ciency but results in a slower transient response. thus, there is a trade - off between the transient response and efficiency. as a guideline, the inductor ripple current , i l , is typically set to one - third of the maximum load current. the inductor value can be calculated by using the following equation: ( ) sw l out in f i d v v l ? ? = where: v in is the input voltage. v out is the output voltage. i l is the inductor ripple current. f sw is the switching frequency. d is the duty cycle. in out v v d =
data sheet adp2325 rev. 0 | page 21 of 32 the adp2325 uses adaptive slope compensation in the current loop to prevent subharmonic oscillations when the duty cycle is larger than 50%. the internal slope compensation limits the min- imum inductor value. for a duty cycle that is larger than 50%, the minimum inductor value is determined by the following equation: ?? sw out f d v ? ?? 2 1 the inductor peak current is calculated by 2 l out peak i ii ? ?? the saturation current of the inductor must be larger than the peak inductor current. for the ferrite core inductors with a quick saturation characteristic, the saturation current rating of the inductor should be higher than the current-limit threshold of the switch to prevent the inductor from entering saturation. the rms current of the inductor can be calculated by 12 2 2 l out rms i ii ? ?? shielded ferrite core materials are recommended for low core loss and low emi. table 9. recommended inductors vendor part no. value (h) i sat (a) i rms (a) dcr (m) sumida cdrh105rnp-0r8n 0.8 13.5 9.5 4.3 cdrh105rnp-1r5n 1.5 10.5 8.3 5.8 cdrh105rnp-2r2n 2.2 9.25 7.5 7.2 cdrh105rnp-3r3n 3.3 7.8 6.5 10.4 cdrh105rnp-4r7n 4.7 6.4 6.1 12.3 cdrh105rnp-6r8n 6.8 5.4 5.4 18 coilcraft mss1048-152nl 1.5 10.5 10.8 5.1 mss1048-222nl 2.2 8.4 9.78 7.2 mss1048-332nl 3.3 7.38 7.22 10.1 mss1048-472nl 4.7 6.46 6.9 11.4 mss1048-682nl 6.8 5.94 6.01 15.4 wurth elektronik 7447797110 1.1 16 7.6 14 7447797180 1.8 13.3 7.3 16 7447797300 3.0 10.5 7.0 18 7447797470 4.7 8.0 5.8 27 7447797620 6.2 7.5 5.5 30 output capacitor selection the output capacitor selection affects both the output voltage ripple and the loop dynamics of the regulator. for example, during load step transient on the output, when the load is sud- denly increased, the output capacitor supplies the load until the control loop can ramp up the inductor current, which causes an undershoot of the output voltage. use the following equation to calculate the output capacitance that is required to meet the voltage droop requirement: ?? out_uv out in step uv out_uv vvv lik c ???? ??? ? 2 2 where: i step is the load step. v out_uv is the allowable undershoot on the output voltage. k uv is a factor, typically setting k uv = 2. another example is when a load is suddenly removed from the output and the energy stored in the inductor rushes into the output capacitor, which causes the output to overshoot. the output capacitance required to meet the overshoot requirement can be calculated using the following equation: ?? 2 2 _ 2 out ovout out step ov out_ov v vv lik c ? ?? ??? ? where: v out_ov is the allowable overshoot on the output voltage. k ov is a factor, typically setting k ov = 2. the output ripple is determined by the esr of the output capacitor and its capacitance value. use the following equation to select a capacitor that can meet the output ripple requirements: out_ripple sw l out_ripple vf i c ??? ? ? 8 l out_ripple esr i v r ? ? ? where: v out_ripple is the allowable output voltage ripple. r esr is the equivalent series resistance of the output capacitor. select the largest output capacitance given by c out_uv , c out_ov , and c out_ripple to meet both load transient and output ripple performance. the selected output capacitor voltage rating must be greater than the output voltage. the minimum rms current rating of the output capacitor is determined by the following equation: 12 _ l rmsc i i out ? ?
adp2325 data sheet rev. 0 | page 22 of 32 low - side power device se lection the adp2325 has integrated low - side mosfet drivers, which can drive the low - side n - channel mosfets (nfets). the selec - tion of the low - side n - channel mosfet affects the dc - to - dc regulator performance. the selected mosfet must meet the following requirements: ? drain source voltage (v ds ) must be higher than 1.2 v in . ? drain current (i d ) must be greater than 1.2 i limit_max , where i limit_max is the selected maximum current - limit threshold. the adp2325 low - side gate drive voltage is 5 v. make sure that the selected mosfet can be fully turned on at 5 v. total gate charge (qg at 5 v) must be less than 50 nc. lower qg characteristics constitute higher efficiency. when the high - side mosfet is turned off, the low - side mosfet carries t he inductor current. for low duty cycle applications, the low - side mosfet carries the current for most of the period. to achieve higher efficiency, it is important to select a low on - resist - ance mosfet. the power conduction loss for the low - side mosfet can be calculated by p fet_low = i out 2 r dson (1 ? d ) where r dson is the on resistance of the low - side mosfet. make sure that the mosfet can handle the thermal dissipation due to the power loss. in some cases, efficiency is not critical for the system; therefore, the diode can be selected as the low - side power device. the average current of the diode can be calculated by i diode (avg) = (1 ? d ) i out the reverse breakdown voltage rating of the di ode must be greater than the input voltage with an appropriate margin to allow for ringing, which may be present at the swx node. a schottky diode is recommended because it has a low forward voltage drop and a fast switching speed. if a diode is used for t he low - side device, the adp2325 must enable the pfm mode by connecting the mode pin to ground. table 10 . recommended mosfets vendor part no. v ds i d r dson qg fairchild FDS8880 30 v 10.7 a 12 m 12 nc fairchild fdms7578 25 v 14 a 8 m 8 nc fairchild fds6898a 20 v 9.4 a 14 m 16 nc vishay si4804cdy 30 v 7.9 a 27 m 7 nc vishay sia430dj 20 v 10.8 a 18.5 m 5.3 nc aos aon7402 30 v 39 a 15 m 7.1 nc aos ao4884l 40 v 10 a 16 m 13.6 nc programming the uvlo input the p recision enable input can be used to program the uvlo threshold and hysteresis of the input voltage , as shown in figure 50 . figure 50 . programming the uvlo input use the following equation to calculate r top_en and r bot_en : a 1 v 2 . 1 a 5 v 1 . 1 v 2 . 1 v 1 . 1 ? ? = in_falling in_rising top_en v v r v 2 . 1 5 v 2 . 1 _ _ _ _ ? ? = en top rising in en top en bot r v r r where: v in_rising is the v in rising threshold. v in_falling is the v in falling threshold. compensation compone nts design in peak current mode control, the power stage can be simplified to a voltage controlled current source supplying current to the output capacitor and load resistor. it is composed of one domain pole and a zero contributed by the output capacitor esr. the control - to - output transfer function is shown in the following equations: ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? + = = p z vi comp out vd f s f s r a s v s v s g 2 1 2 1 ) ( ) ( ) ( out esr z c r f = 2 1 ( ) out esr p c r r f + = 2 1 where: a vi = 8.33 a/v . r is the load resistance. c out is the output capacitance. r esr is the equivalent series resistance of the output capacitor. enx 1.2v en cmp 4a 1a pvinx r top_en r bot_en 10036-046
data sheet adp2325 rev. 0 | page 23 of 32 the adp2325 uses a transconductance amplifier for the error amplifier to compensate the system. figure 51 shows the simplified peak current mode control small signal circuit. figure 51 . simplified peak current mode control small signal circuit the compensation components, r c and c c , contribute a zero, and the optional c cp and r c contribute an optional pole. the closed - loop transfer equation is as follows: (s) g s c c c c r s s c r c c g r r r (s) t vd cp c cp c c c c cp c m top bot bot v ? ? ? ? ? ? ? ? + + + + ? + = 1 1 the fol lowing design guideline s show how to select the compen - sation co mponents, r c , c c , and c cp , for ceramic output capacitor applications. 4. determine the cross frequency (f c ). generally, the f c is between f sw /12 and f sw /6. 5. r c can be calculated by using the following equation: vi m c out out c a g f c v r = v 6 . 0 2 6. place the compensation zero at the domain pole (f p ). c c can be determined by ( ) c out esr c r c r r c + = 7. c cp is optional. it can be used to cancel the zero caused by the esr of the output capacitor. c out esr cp r c r c = the adp2325 has a n internal 10 pf capacitor at the compx pin; therefore, if c cp is smaller than 10 pf, no external capacitor is requir ed. r esr r + ? g m r c c cp c out c c r top r bot ? + a vi v out v comp v out 10036-047
adp2325 data sheet rev. 0 | page 24 of 32 design example this section describe s the design procedure and component selection for the example application shown in figure 54 , an d table 11 provides a list of the required settings. table 11 . dual step - down dc - to - dc regulator requirements parameter specification channel 1 input voltage v in1 = 12.0 v 10% output voltage v out1 = 1.2 v output current i out1 = 5 a output voltage ripple v out1_ripple = 12 mv load transient 5%, 1 a to 4 a, 1 a/s channel 2 input voltage v in2 = 12.0 v 10% output voltage v out2 = 3.3 v output current i out2 = 5 a output voltage ripple v out2_ripple = 33 mv load transient 5%, 1 a to 4 a, 1 a/s switching frequency f sw = 500 khz output voltage setti ng choose a 10 k? top feedback resistor (r top ); calculate the bottom feedback resistor using the following equation: ? ? ? ? ? ? ? ? ? = 6 . 0 6 . 0 out top bot v r r to set the output voltage to 1.2 v, the resistor values are r top1 = 10 k? and r bot1 = 10 k?. to set the output voltage to 3.3 v, the resistors values are r top2 = 10 k? and r b ot2 = 2.21 k?. current - limit setting for 5 a output current operation, the typical peak current limit is 8 a. in this case, no r ilim is required. frequency setting to set the switching frequency to 500 khz, use the following equation to calculate the resis tor value, r osc : ( ) ( ) khz 000 , 60 k sw osc f r = therefore, r osc =120 k?. inductor selection the peak - to - peak inductor ripple current, i l , is set to 30% of the maximum output current. use the following equation to estimate the value of the inductor: ( ) sw l out in f i d v v l ? ? = for v out1 = 1.2 v, inductor l1 = 1.4 h, and for v out2 = 3.3 v, inductor l2 = 3.2 h. select the standard inductor value of 1.5 h and 3.3 h for the 1.2 v and 3.3 v rails. calculate the peak - to - peak inductor ripple current as follows: ( ) sw out in l f l d v v i ? = ? for v out1 = 1.2 v, i l1 = 1.44 a. for v out2 = 3.3 v, i l2 = 1.45 a. find the peak inductor current using the following equation: 2 l out peak i i i ? + = for the 1.2 v rail, the peak inductor current is 5.73 a, and for the 3.3 v rail, t he peak inductor current is 5.73 a. the rms current through the inductor can be estimated by 12 2 2 l out rms i i i ? + = the rms current of the inductor for both the 1.2 v and 3.3 v rails is approximately 5.02 a. for the 1.2 v rail, select an inductor with a m inimum rms current rating of 5.01 a and a minimum saturation current rating of 5.73 a. for the 3.3 v rail, select an inductor with a minimum rms current rating of 5.02 a and a minimum saturation current rating of 5.73 a. based on these requirements, for th e 1.2 v rail, select a 1.5 h inductor, such as the sumida cdrh105rnp - 1r5n, with a dcr = 5.8 m?; for the 3.3 v rail, select a 3.3 h inductor, such as the sumida cdrh105rnp - 3r3n, with a dcr = 10.4 m? . output capacitor sel ection the output capacitor is required to meet the output voltage ripple and load transient requirement s . to meet the output voltage ripple requirement, use the following equation to calculate the capacitance and esr: ripple out sw l out_ripple v f i c _ 8 ? ? = l ripple out esr i v r _ ? = for v out1 = 1.2 v, c out_ripple1 = 30 f and r esr1 = 8.3 m?. for v out2 = 3.3 v, c out_ripple2 = 11 f and r esr2 = 23 m?.
data sheet adp2325 rev. 0 | page 25 of 32 to meet the 5% overshoot and undershoot requirement, use the following equation to calculate the capacitance: ( ) 2 2 _ 2 out ov out out step ov out_ov v v v l i k c ? ? + ? = ( ) uv out out in step uv out_uv v v v l i k c _ 2 2 ? ? ? = for estimation purposes, use k ov = k uv = 2. for v out1 = 1.2 v, use c out_ov1 = 188 f and c out_uv1 = 21 f. for v out2 = 3.3 v, use c out_ov2 = 55 f and c out_uv2 = 21 f. fo r the 1.2 v rail, esr of the output capacitor must be smaller than 8.3 m?, and the output capacitance must be larger than 188 f. it is recommend that three 100 f , x5r , 6.3 v ceramic capacitor s be used, such as the grm32er60j107me20 from murata, with an esr = 2 m?. for the 3.3 v rail, the esr of the output capacitor must be smaller than 23 m? , and the output capacitance must be larger than 55 f. it is recommended that two 47 f , x5r , 6. 3 v ceramic capacitor s be used, such as the murata grm32er60j476me20, with an esr = 2 m?. low - side mosfet selectio n a low r dson n - channel mosfet is selec ted for high efficiency solutions. the mosfet breakdown voltage must be greater than 1.2 v v in , and the drain current must be greater than 1.2 v i limit . it is recommended that a 30 v, n - channel mosfet be used, such as the FDS8880 from fairchild. the r d son of the FDS8880 at a 4.5 v driver voltage is 12 m?, and the total gate charge is 12 nc. compensation compone nts for better load transient and stability performance, set the cross frequency, f c , to f sw /10. in this case, f sw runs at 500 khz; therefore, th e f c is set to 50 khz. for the 1.2 v rail, the 100 f ceramic output capacitor has a derated value of 64 f. k 9 . 28 a/v 8.33 s 500 v 0.6 khz 50 f 64 3 v 2 . 1 2 = = c1 r ( ) pf 1598 k 9 . 28 f 64 3 001 . 0 24 . 0 = + = c1 c pf 6 . 6 k 9 . 28 f 64 3 001 . 0 = = cp1 c by c hoosing standard components where r c1 = 28 k? and c c1 = 1500 pf , n o c cp1 is needed. figure 52 shows the 1.2 v rail bode plot at 5 a. the cross frequency is 42 khz and the phase margin is 50. figure 52 . bode plot for 1.2 v rail for the 3.3 v rail, the 47 f ceramic output capacitor has a derated value of 32 f. k 5 . 26 a/v 8.33 s 500 v 0.6 khz 50 f 2 3 2 v 3 . 3 2 = = c2 r ( ) pf 1594 k 5 . 26 f 32 2 001 . 0 66 . 0 = + = c2 c pf 4 . 2 k 5 . 26 f 32 2 001 . 0 = = cp2 c by using standard component values of r c2 = 27 k? and c c2 = 1500 pf , n o c cp2 is needed. figure 53 shows the 3.3 v rail bode plot at 5 a. the cross frequency is 55 khz and phase margin is 67. figure 53 . bode plot for 3.3 v rail 1k ?60 60 ?48 48 ?36 ?24 ?12 12 24 36 magnitude (db) phase (degrees) frequenc y (hz) 0 ?180 180 ?144 144 ?108 ?72 ?36 36 72 108 0 10k 100k 1 2 1m 10036-061 1k ?60 60 ?48 48 ?36 ?24 ?12 12 24 36 magnitude (db) phase (degrees) frequenc y (hz) 0 ?180 180 ?144 144 ?108 ?72 ?36 36 72 108 0 10k 100k 1 2 1m 10036-062
adp2325 data sheet rev. 0 | page 26 of 32 soft start time programming the soft start feature allows the output voltage to ramp up in a con trolled manner, eliminating output voltage overshoot during soft start and limiting inrush current. the soft start time is set to 3 ms. nf 5 . 17 v 6 . 0 ms 3 a 5 . 3 v 6 . 0 = = = ss ss ss t i c choose a standard component value of c ss1 = c ss2 = 22 nf. input capacitor sele ction a minimum 10 f ceramic capacitor is required, placed near the pvinx pin. in this application, one x5r ceramic capacitor of 10 f and 25 v is recommended.
data sheet adp2325 rev. 0 | page 27 of 32 external components recommendation s table 12 . recommended external components for typical applications with 5 a output current f sw (khz) v in (v) v out (v) l (h) c out (f) 1 r top (k) r bot (k) r c (k) c c (pf) c cp (pf) 300 12 1 2.2 2 330 10 15 47 2700 56 12 1.2 2.2 2 330 10 10 59 2700 56 12 1.5 3.3 2 330 15 10 75 2700 47 12 1.8 3.3 330 20 10 43 2700 68 12 2.5 4.7 330 47.5 15 62 2700 56 12 3.3 4.7 2 100 10 2.21 33 2700 3.3 12 5 6.8 100 + 47 22 3 36 2700 3.3 5 1 1.5 2 330 10 15 49 2700 68 5 1.2 2.2 2 330 10 10 59 2700 56 5 1.5 2.2 330 15 10 37 2700 82 5 1.8 2.2 330 20 10 43 2700 68 5 2.5 2.2 2 100 47.5 15 22 2700 4.7 5 3.3 2.2 100 10 2.21 15 2700 4.7 600 12 1.5 1.5 330 15 10 75 1500 47 12 1.8 1.5 3 100 20 10 53 1500 2.2 12 2.5 2.2 2 100 47.5 15 47 1500 2.2 12 3.3 2.2 100 + 47 10 2.21 47 1500 2.2 12 5 3.3 100 22 3 47 1500 2.2 5 1 1 330 10 15 49 1500 68 5 1.2 1 330 10 10 59 1500 56 5 1.5 1 2 100 15 10 27 1500 4.7 5 1.8 1.5 2 100 20 10 33 1500 3.3 5 2.5 1.5 100 + 47 47.5 15 33 1500 2.2 5 3.3 1.5 100 10 2.21 30 1500 4.7 1000 12 1.8 1 2 100 20 10 56 820 2.2 12 2.5 1 100 47.5 15 39 820 2.2 12 3.3 1.5 100 10 2.21 53 820 2.2 12 5 2 47 22 3 39 820 2.2 5 1 0.56 3 100 10 15 47 820 2.2 5 1.2 0.56 2 100 10 10 37 820 6.8 5 1.5 0.68 2 100 15 10 47 820 4.7 5 1.8 0.8 100 + 47 20 10 43 820 4.7 5 2.5 0.8 100 47.5 15 43 820 4.7 5 3.3 0.8 47 10 2.21 27 820 2.2 1 330 f: 6.3 v, sanyo 6tpd330m; 100 f: 6.3 v, x5r, murata grm32er60j107me20; 47 f: 6.3 v, x5r, murata grm32er60j476me20.
adp2325 data sheet rev. 0 | page 28 of 32 typical application circuits figure 54 . using an external mosfet application, v in1 = v in2 = 12 v, v out1 = 1.2 v, i out1 = 5 a, v out2 = 3.3 v, i out2 = 5 a, f sw = 500 khz figure 55 . using an external diode application, v in1 = v in2 = 12 v, v out1 = 5 v, i out1 = 3 a, v out2 = 3.3 v, i out2 = 1.5 a, f sw = 600 kh z bst1 pvin1 sw1 dl1 pgnd sw2 dl2 en1 pgood1 ss1 comp1 fb1 bst2 pvin2 en2 ss2 comp2 fb2 pgood2 gnd sync scfg intvcc rt vdrv v out2 3.3v 5a v out1 1.2v 5a v in 12v adp2325 l1 1.5 h l2 3.3 h c out1 100 f c out4 47 f c out2 100 f c out3 100 f c out5 47 f c in1 10f, 25v m1 FDS8880 m2 FDS8880 r osc 120k? c bst1 0.1 f c ss2 22nf c c2 1500 pf r c2 27k? r top1 10k? r bot2 2.21k? r top2 10k? c int 1f c drv 1f trk1 trk2 mode v in 12v c in2 10 f, 25v c bst2 0.1 f r bot1 10k? r c1 28k? c c1 1500pf c ss1 22nf 10036-050 bst1 pvin1 sw1 dl1 pgnd sw2 dl2 en1 pgood1 ss1 comp1 fb1 bst2 pvin2 en2 ss2 comp2 fb2 pgood2 gnd sync scfg intvcc rt vdrv v out2 3.3v 1.5a v out1 5v 3a v in 12v adp2325 l1 4.7 h l2 8.2 h c out1 22 f c out3 22 f d2 b220a d1 b320b c out2 22 f c out4 22 f c in1 10f, 25v r osc 100k? c bst1 0.1 f c ss2 10nf c c2 4.7nf r c2 18k? r ilim1 47k? r ilim2 47k? r top1 22k? r bot2 2.21k? r top2 10k? c int 1f c drv 1f trk1 trk2 v in 12v c in2 10 f, 25v c bst2 0.1 f r bot1 3k? r c1 20k? c c1 2.2nf mode c ss1 10nf 10036-051
data sheet adp2325 rev. 0 | page 29 of 32 figure 56 . parallel single output application, v in = 12 v, v out = 1.2 v, i out = 10 a, f sw = 300 khz figure 57 . enable pfm mode with the mode pin pulled to gnd, v in1 = v in2 = 12 v, v out1 = 1.5 v, i out1 = 5 a, v out2 = 2.5 v, i out2 = 5 a, f sw = 600 khz trk1 r t op1 10k? c c1 1200pf c cp1 56pf r c1 59k? r osc 200k? c ss1 22nf c int 1f c in1 10 f , 25v c bst1 0.1f c bst2 0.1f l1 1h m1 FDS8880 m2 FDS8880 l2 1h v in 12v v in 12v v out1 1.2 v , 10 a c out1 330f r bot1 10k? c in2 10 f , 25v fb1 comp1 ss1 en1 pvin1 bst1 fb2 comp2 ss2 en2 pvin2 pvin2 bst2 pgood1 scfg sync intvcc adp2325 rt mode pgood2 trk2 gnd sw1 sw1 sw2 dl1 pgnd dl2 sw2 vdr v pvin1 c out2 330f c out3 10f c dr v 1f 10036-052 intvcc r t op1 15k? c c1 1200pf r c1 47k? c ss1 22nf c int 1f c dr v 1f c in1 10 f , 25v c bst1 0.1f c bst2 0.1f l1 1.5h l2 2.2h v in 12v v out1 1.5 v , 5a c out4 47f v in 12v r bot1 10k? r t op2 47.5k? r c2 39k? c c2 1200pf c ss2 22nf c in2 10 f , 25v r bot2 15k? r osc 100k? fb1 comp1 ss1 en1 pvin1 bst1 fb2 comp2 ss2 en2 pvin2 bst2 mode scfg trk2 trk1 vdr v adp2325 gnd pgood2 pgood1 sync rt sw1 dl1 pgnd dl2 sw2 c out2 100f c out5 47f c out1 100f c out3 100f c out6 47f m1 FDS8880 m2 FDS8880 v out1 2.5 v , 5a 10036-053
adp2325 data sheet rev. 0 | page 30 of 32 figure 58 . synchronization with 90 phase shift betwe en each channel intvcc r t op1 20k? c c1 1200pf r c1 53k? c ss1 22nf c int1 1f c dr v1 1f c in1 10 f , 25v c bst1 0.1f c bst2 0.1f l1 1.5h m1 FDS8880 m2 FDS8880 l2 2.2h v in 12v v in 12v v out1 1.8 v , 3a c out1 100f c out4 100f v out2 3.3 v , 5a r bot1 10k? r t op2 10k? r c2 62k? c c2 1200pf c ss2 22nf c in2 10 f , 25v r bot2 2.21k? r osc1 100k? fb1 comp1 ss1 en1 pvin1 bst1 fb2 comp2 ss2 en2 pvin2 bst2 mode scfg trk2 trk1 vdr v adp2325 gnd pgood2 pgood1 rt sw1 dl1 pgnd dl2 sw2 c out2 100f c out5 100f intvcc sync sync r t op3 20k? c c3 1200pf r c3 53k? c ss3 22nf c int2 1f c dr v2 1f c in3 10 f , 25v c bst3 0.1f c bst4 0.1f l3 1.5h m3 FDS8880 m4 FDS8880 l4 2.2h v in 12v v in 12v v out3 1.8 v , 3a c out6 100f c out9 100f v out4 3.3 v , 5a r bot3 10k? r t op4 10k? r c4 62k? c c4 1200pf c ss4 22nf c in4 10 f , 25v r bot4 2.21k? r osc2 120k? fb1 comp1 ss1 en1 pvin1 bst1 fb2 comp2 ss2 en2 pvin2 bst2 mode scfg trk2 trk1 vdr v adp2325 gnd pgood2 pgood1 rt sw1 dl1 pgnd dl2 sw2 c out7 100f c out10 100f c out8 100f c out3 100f 10036-054
data sheet adp2325 rev. 0 | page 31 of 32 figure 59 . programmable v in_rising = 8.7 v, v in_falling = 6.7 v, 3.3 v startu p prior to 1.8 v, v in1 = v in2 = 12 v, v out1 = 3.3 v, i out1 = 5 a, v out2 = 1.8 v, i out2 = 5 a, f sw = 300 khz figure 60 . channel 2 tracking with channel 1 v in1 = v in2 = 12 v, v out1 = 2.5 v, i out1 = 5 a, v out2 = 1.25 v, i out2 = 5 a, f sw = 500 khz intvcc r t op1 10k? c c1 2200pf r c1 47k? r en_bot 68k? r en_ t op 330k? c ss1 22nf c int 1f c dr v 1f c in1 10 f , 25v c bst1 0.1f c bst2 0.1f l1 4.7h m1 FDS8880 m2 FDS8880 l2 3.3h v in 12v v in 12v v out1 3.3 v , 5a c out1 100f c out4 330f v out2 1.8 v , 5a r bot1 2.21k? r t op2 20k? r c2 82k? c c2 2200pf c cp2 36pf c in2 10 f , 25v r bot2 10k? r pgood1 100k? r osc 200k? fb1 comp1 ss1 en1 pvin1 bst1 fb2 comp2 ss2 en2 pvin2 bst2 scfg trk2 trk1 vdr v adp2325 gnd rt sw1 dl1 pgnd dl2 sw2 c ss2 22nf mode pgood2 pgood1 sync c out2 100f c out5 330f c out3 100f 10036-055 intvcc r t op1 47.5k? r trk_ t op 47.5k? r trk_bot 15k? c c1 1200pf r c1 33k? c ss1 22nf c int 1f c dr v 1f c in1 10 f , 25v c bst1 0.1f c bst2 0.1f l1 2.2h m1 FDS8880 m2 FDS8880 l2 1.5h v in 12v v in 12v v out1 2.5 v , 5a c out1 47f c out4 330f v out2 1.25 v , 5a r bot1 15k? r t op2 13k? r c2 49k? c c2 1500pf c cp2 56pf c ss2 10nf c in2 10 f , 25v r bot2 12k? r osc 120k? fb1 comp1 ss1 en1 pvin1 bst1 fb2 comp2 ss2 en2 pvin2 bst2 mode scfg trk1 vdr v adp2325 gnd pgood2 pgood1 trk2 rt sw1 dl1 pgnd dl2 sw2 sync c out2 47f c out5 10f c out3 47f 10036-056
adp2325 data sheet rev. 0 | page 32 of 32 packag ing and ordering information outline dimensions figure 61 . 32 - lead lead frame chip scale package [lfcsp_wq] 5 mm 5 mm body, very very thin quad (cp - 32 - 7) dimensions shown in millimeters ordering guide model 1 temperature range output voltage package description 2 package option adp2325acpz - r7 ?40c to +125c adjustable 32 - lead lfcsp_wq cp - 32 - 7 adp2325 - evalz evaluation board adp2325 - bl1 - evz blank dual output evaluation board adp2325 - bl2 - evz blank single output evaluation board 1 z = rohs compliant part. 2 for the blank evaluation boards, user s can request an unpopulated board from analog devices, inc., through the adisimpower tool found at www.analog.com/adisimpower , as well as generate schematics and a b il l of materials from the tool . compliant to jedec standards mo-220-whhd. 112408-a 1 0.50 bsc bot t om view top view pin 1 indic a t or 32 9 16 17 24 25 8 exposed pa d pin 1 indic a t or 3.25 3.10 sq 2.95 sea ting plane 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.30 0.25 0.18 5.10 5.00 sq 4.90 0.80 0.75 0.70 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.50 0.40 0.30 0.25 min ? 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d10036 - 0- 2/12(0) www.analog.com/ adp2325

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